Research

[POSTECH Research Team Led by Prof. Byoung Hun Lee Overcomes Performance Limits 

of Ultra-Thin Semiconductors with a Novel Localized Thick-Contact Design]

 As semiconductor chips become increasingly thinner, the components inside chips are locked in a fierce race to achieve the ultimate ultra-thin state. However, this has presented a structural limitation: the thinner the device, the harder it is for electricity to flow. Recently, a research team at POSTECH  successfully resolved this issue through a simple yet innovative approach: "thickening only the necessary parts."

The research team, led by Professor Byoung Hun Lee from POSTECH’s Department of Electrical Engineering and the Department of Semiconductor Engineering, has developed a technology that dramatically lowers contact resistance by redesigning the metal-semiconductor contact structure in ultra-thin tellurium (Te) transistors. This breakthrough was recently published in ACS Nano, a prominent international journal in the field of nanotechnology.

With the rapid advancement of artificial intelligence (AI) and high-performance computing, the volume of data that semiconductors must process is surging. Consequently, the time and energy loss occurring between the "logic" (which handles computations) and "memory" (which stores data) have been identified as a major bottleneck. To address this, 3D integrated structures that stack logic and memory vertically are gaining significant traction as a next-generation technology. Fabricating these structures requires devices that can operate stably even at temperatures below 400°C.

Tellurium (Te) is highly regarded as a strong candidate for semiconductor channel material due to its high charge mobility, room-temperature stability, and low-temperature processability. However, its narrow band gap makes it prone to "leakage current," where current leaks even when the transistor is turned off. To minimize this, the channel must be fabricated to an ultra-thin thickness of under 5 nanometers (nm) to precisely control electron transport.

The dilemma arises because when the channel becomes too thin, electron transport across the interface between the metal electrode and the semiconductor becomes severely restricted. A Schottky barrier—an energy barrier that electrons must cross between the metal and semiconductor—grows larger as the channel gets thinner. Ultimately, while researchers could reduce leakage current, doing so simultaneously increased contact resistance, significantly degrading device performance.

To overcome this, the POSTECH team applied the 'Raised Source and Drain (RSD)' structure, a technique conventionally used in silicon processes. The core idea is to deposit additional tellurium to thicken only the areas directly in contact with the electrodes where the current enters and exits (the source and drain). By keeping the current-flowing channel at a thin 4 nm to suppress leakage current while adding extra tellurium to the sections in contact with the metal electrodes, the team allowed the current to flow with significantly improved efficiency.

Experimental results demonstrated that devices utilizing this structure experienced a dramatic 50-fold reduction in contact resistance, dropping from 97.5 kΩ·μm to 1.7 kΩ·μm. Furthermore, in an extreme environment of -196°C, the on-state current when the device was fully turned on increased by more than 17 times. The team effectively succeeded in simultaneously achieving both low resistance and high performance within an ultra-thin structure. Notably, this technology can be implemented through a large-area, low-temperature deposition process known as sputtering, ensuring the high scalability required for actual semiconductor mass production.

"We have broken through the chronic dilemma of ultra-thin semiconductors—where thinner channels traditionally resulted in higher resistance—with a novel band engineering approach called 'localized thickness control,'" said Professor Byoung Hun Lee of POSTECH. "We expect this to become a core platform technology that can be widely applied not only to tellurium but also to enhancing the performance of various 2D and ultra-thin semiconductor devices, ultimately accelerating the realization of next-generation 3D integrated circuits."

This work was supported by the Nanomaterials Development Program and the Core Technology Development Project for National Semiconductor Research Laboratory through the National Research Foundation (NRF) funded by the Ministry of Science and ICT (MSIT), Korea.

▶️ DOI: https://doi.org/10.1021/acsnano.5c18395